Packaging Coprocessor as an IP

The following procedure describes how the coprocessor of Lab 1 can be packaged as an IP which can be used in the IP Integrator. A more tedious alternative will be to make the connections yourself using HDL in the wrapper.

There could be slight differences in what you see based on the version of Vivado, but the spirit of the instructions below remains the same.

We can continue from the hardware platform project from Lab 2 as shown below. You could also package the IP in a separate project rather than in the Lab 2 project. The packaged IP can be imported into the project you want it in (e.g., the Lab 2 project). Either way, the steps for packaging are the same.

The exact block diagram will vary for you depending on whether or not you included other peripherals for Lab 2 (e.g., AXI Stream FIFO, AXI Timer), but does not fundamentally change how you package the coprocessor as an IP - the exact peripherals and connections can be changed later. 

Select Tool (Vivado top menu) → Create and Package IP. The Create and Package IP dialog will appear. Click Next.

Select Create a New AXI4 Peripheral and Next, you may use the default settings. Next again.

You will now be presented with an interface. It is entirely possible to configure this page properly (e.g., by choosing Stream, Slave, and then adding a Stream, Master) and get a template for an AXI Stream co-processor. However, the template provided is rather complex. So we will be just using the lab 1 template rather than relying on the template generated by Vivado. So we just accept the defaults (which is a peripheral with an AXI Lite slave interface) and click Next and Finish.

Now we can add our custom IP to the design. Choose Add IP (the + button in the IP Integrator canvas, or right-click anywhere on the canvas and Add IP) and search for myip. If myip_v1_0 (the coprocessor) is not available in the IP catalog, it means the custom IP folder is not local to the project, and you need to add the folder containing it to the IP repository. This can be done by right-clicking on the IP integrator canvas, IP settings > IP > Repository.

Do NOT make any connections to the added IP as yet.

We need to modify our custom IP. Right-click on the block, and select Edit in IP Packager. Vivado will create another Vivado project to edit the IP just like the one you worked on in Lab 1. The default location will be inside your project folder, .tmp folder. Click OK.

Remove myip_v1_0_S00_AXI.v/vhd (Right-click and 'Remove File from the Project'). Copy-paste the content of myip_v1_0.v/vhd from the original Lab 1 template to overwrite the Vivado-created myip_v1_0.v/vhd contents.

Now, right-click Design Sources > Add Sources > Add or create design sources > Next > Add Files > Browse to and select matrix_multiply.v/vhd and memory_RAM.v/vhd, from the original Lab 1 templates. Check the option 'Copy sources into IP directory' and uncheck 'Scan and add RTL include files into project' (this will keep the files in the IP directory, which is a good idea) > OK > Finish.

Note: It is also ok to remove the auto-generated myip_v1_0.v/vhd and add myip_v1_0.v/vhd along with matrix_multiply.v/vhd and memory_RAM.v/vhd. However, Vivado will ask for a top-level module when both the auto-generated files are removed which you can dismiss by accepting the default selection and clicking OK. In the future, when you wish to modify the original files, it is better to replace the original contents with the new contents rather than remove the file altogether and then add back the updated version.

Make sure that myip_v1_0 is the top module, if it is not picked up automatically. The design sources folder should look like how it was for Lab 1.

We now have to reconfigure the IP configurations to allow the original Vivado project to recognize the new IP interfaces correctly. You can notice that some of the green check marks that were originally there are now gone from the Package IP - myip tab (if you closed the tab, it can be reopened from Design Sources > IP-XACT > component.xml), under Packaging Steps. Here, select File Groups, and click Merge changes from File Groups Wizard.

Now click Customization Parameters, and click 'Merge changes ...'.. Right-click and remove C_S00_AXI_BASEADDR and C_S00_AXI_HIGHADDR  (this is a vestige of our original selection of a AXI memory-mapped slave as the IP).

Now click Ports and Interfaces, and click 'Merge changes ...'.

Select the 4 signals starting with S_AXIS (via Ctrl+click or Shift+Click). Right-click and select Auto Infer Interface. In the dialog that opens up, select AXI > axis_rtl and click OK.

In the next dialog, the name S_AXIS will be autodetected (you can change the name if you wish), and verify that the Mode is salve. Click OK.

Do the same for the 4 M_AXIS signals, and verify that the Mode is master.

No, do the same for ARESETN and ACLK, and select Signal>reset_rtl and Signal>clock_rtl respectively.

In the Addressing and Memory tab, right-click on S00_AXI and select Remove Memory Map (this is a vestige of our original selection of a AXI memory-mapped slave as the IP).

Now, go to Review and Package, and click Re-Package IP, and click OK.

You can see that only 1 warning remains (irrelevant/old warnings can be removed by right-clicking messages and selecting Discard User Created Messages) - [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. This is ok.

You can now close the temporary project and go back to the original project with the block design.

Rerun the IP Status Report.

Refresh IP Catalog.

Click Upgrade Selected.

Generate Output Products will pop up. Select Generate.

At this point, you will get some errors and critical warnings, but that is ok. Click Rerun for IP Status Report.

Now, if you discard old warnings and errors, you will see that there are no more critical warnings and errors. The block interfaces for our custom IP would have changed to 

AXI Stream is just a simplex (data flows only in one direction for a link), master-slave, synchronous, point-to-point link with no addressing. The AXI bus, on the other hand, is a bi-directional addressable memory-mapped interface with the main processor as the master. We need a bridge between AXI and AXIS to allow the main processor to send and receive data from the coprocessor. There are 2 options for us - AXI Stream FIFO and AXI DMA. The former is simpler, and perhaps good enough for smaller data sets. However, for larger data, the latter is more efficient, though more complicated from a hardware as well as software perspective. It is a good idea to try AXI Stream FIFO first, before trying out AXI DMA (optional, but strongly recommended for performance and experience).

AXI Stream FIFO and AXI DMA both perform MM2S and S2MM operations. MM2S stands for Memory-Mapped to Stream, where 'memory-mapped' refers to the connection using the AXI interface, where every peripheral is identified using a unique address range (memory-mapped input-output). S2MM, as you can guess easily, is Stream to Memory-Mapped.